DM9601

USB to Ethernet MAC Controller with Integrated 10/100 PHY

Preliminary

Version: DM9601-DS-P01
June 22, 2001

General Description

The DM9601 is a fully integrated and cost-effective
single chip USB to Fast Ethernet MAC controller with
10/100 PHY. It is designed with the low power and
high performance process. It is a 3.3V device with 5V
tolerance then it supports 3.3V and 5V signaling.

The DM9601 provides USB transceiver compliant with
USB1.1, 10/100M PHY, MAC controller, memory
controller and an external MII interface to connect
HPNA device or other support MII interface
transceiver. This chip already integrated 16K byte

SRAM. The DM9601 interfaces to the UTP3, 4, 5 in
10Base-T and UTP5 in 100Base-TX. It is fully compliance
with the IEEE 802.3u Spec. Its auto-negotiation function will
automatically configure the DM9601 to take the maximum
advantage of its abilities. The DM9601 is also support IEEE
802.3x full-duplex flow control.

The DM9601 supports 3 wake-up event to wake-up system
from suspend mode. There are 7 GPIO pins (General
purpose I/O) for user's application.

Block Diagram

EEPROM

Interface

External MII

Interface

LED

TX+/-

RX+/-

MII Management

Control

& MII Register

Autonegotiation

Memory
Management

RX Machine

TX Machine

MAC

MII

100 Base-TX

PCS

100 Base-TX

transceiver

10 Base-T

Tx/Rx

PHYceiver

Control &Status

Registers

Internal

SRAM

EP / SI

con

t
roll

Tx/R

DM9601

USB to Ethernet MAC Controller with Integrated 10/100 PHY

Preliminary

Version: DM9601-DS-P01

June 22, 2001

Features

USB Characteristics:

USB Specification revision 1.1 compliant

Supports 12MHz Full-Speed operation

Supports suspend mode and remote wake-up

resume

Supports USB standard commands

Supports vendor specific commands

Supports test-mode for memory test.

Efficient TX/RX FIFO auto management.

Transceiver:

10/100M

PHY

USB

1.1

Others:

Supports large internal 16K byte SRAM

Supports automatically load vendor ID and

product ID from EEPROM

Supports MII and reverse MII interface

IEEE802.3x flow control for full-duplex mode

Back Pressure Mode for half-duplex mode flow

control

Supports wakeup frame, link status change and

Magic packet events for remote wake-up

Low-Power, Single-Supply 3.3V CMOS

technology

Very Low Power Consumption mode

Power Reduced mode(cable detection)

Power

Down

mode

Selectable TX drivers for 1:1 or 1.25:1

transformers for additional power reduction.

Compatible with 3.3V and 5.0V tolerant I/O

100-pin

LQFP

DM9601

USB to Ethernet MAC Controller with Integrated 10/100 PHY

Preliminary

Version: DM9601-DS-P01
June 22, 2001

Pin Configuration: 100 Pin LQFP & with MII Interface Mode

DM9601

48
47

44
43
42
41
40

37
36

35
34
33
32
31
30

28
27

89
90
91

95
96

98
99

100

BGRES

AGND

LINK_O

WAKEUP

PW_RST#

DGND

77
78
79
80
81
82
83
84
85

GPIO4
GPIO5
GPIO6

NC
NC
NC

DVDD

NC
NC

NC
NC
NC

DGND

DVD

EST

DVD

AVDD

RX+

RX-

AGND

TXO+

TXO-

AVDD

DVDD

LINK_I

RXD0

RXD1

RXD2

RXD3

DGND

CRS

COL

RX_DV

RX_ER

RX_CLK

TEST5

TX_CLK

TXD0

I
O

DGN

PEED

LIN

DGN

I
O

DM9601

USB to Ethernet MAC Controller with Integrated 10/100 PHY

Preliminary

Version: DM9601-DS-P01

June 22, 2001

Pin Description

Pin No.

Pin Name

Type

Description

MII Interface

LINK_I

I/O

External MII device link status.

38,39,40,

RXD[3:0]

I/O

External MII Receive Data

CRS

I/O

External MII Carrier Sense

COL

I/O

External MII Collision Detect

RX_DV

I/O

External MII Receive Data Valid

RX_ER

I/O

External MII Receive Error

RX_CLK

I/O

External MII Receive Clock

TX_CLK

I/O

External MII Transmit Clock

50,51,52,

TXD[3:0]

I/O

External MII Transmit Data

TX_EN

I/O

External MII Transmit Enable

MDIO

I/O

MII Serial Management Data

MDC

I/O

MII Serial Management Data Clock

EEPROM Interface

EEDI

I/O

Data from EEPROM

EEDO

I/O

Data to EEPROM

EECK

I/O

Clock to EEPROM

EECS

Chip Select to EEPROM
This pin is used as a strap pin to define the LED modes.
When it is pull-high, the LED mode is the mode 1;
Otherwise it is mode 0.

USB Interface

I/O

USB Data Minus

I/O

USB Data Plus

Clock Interface

X2_25M

I/O

Crystal 25MHz Out

X1_25M

I/O

Crystal 25MHz In

CLK20MO

I/O

20Mhz clock output

LED Interface

SPEED100#

Speed LED
It is low output to indicate that the internal PHY is operated in 100M
speed, or it is floating for the 10M mode of the internal PHY.

DUP#

Full-duplex LED
In LED mode 1, It is low output to indicate that the internal PHY is

DM9601

USB to Ethernet MAC Controller with Integrated 10/100 PHY

Preliminary

Version: DM9601-DS-P01
June 22, 2001

operated in full-duplex mode, or it is floating for the half-duplex mode of
the internal PHY.
In LED mode 0, It is low output to indicate that the internal PHY is
operated in 10M mode, or it is floating for the 100M mode of the internal
PHY.

LINK&ACT#

Link LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY.
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only.

10/100 PHY/Fiber

Fiber-optic signal detect
PECL signal which indicates whether or not the fiber-optic receives pair
is receiving valid levels.

AGND

Bandgap ground.

BGRES

I/O

Bandgap pin.

AVDD

Bandgap and guard ring power

AVDD

RX power

RX+

TP RX input

RX-

TP RX input

AGND

RX ground

AGND

TX ground

TXO+

TP TX output

TXO-

TP TX output

AVDD

TX power

Miscellaneous

16,17,18

TEST1~TEST4

Operation Mode, tie to ground in application.
Tie TEST1 to high if external PHY is used.

TEST5

It must be ground.

68,69,70,
71,82,83,

GPIO0~6

I/O

General I/O ports
Registers GPCR and GPR can program these pins.
The GPIO0 is output mode with output data high at default to power
down internal PHY and other external MII device.
GPIO1~6 default are input ports.

LINK_O

Cable link status output. Active High.
This pin is also used as a strap pin to define the MII interface is reversed
MII interface (pull-high) or normal MII interface (not pull-high).

WAKEUP

Issue a wake-up signal when wake-up event happens.

PW_RST#

Hardware Reset
Active low signal to initiate the DM9601.

1,2,3,4,6,7,

8,9,10,11,

12,13,14,
77,85,86,
87,88,89,

Not Connect

Электронный компонент: DM9601E